An integrated circuit is a compact semiconductor device containing transistors, resistors, capacitors, and their interconnections, all fabricated on a single piece of silicon smaller than a fingernail. Silicon dominates the industry not because it is the best conductor โ copper and silver far exceed it โ but because it is the most practical: abundant in ordinary silica sand, thermally stable, and uniquely controllable. Adding trace impurities shifts silicon from near-insulator to conductor with precise and repeatable electrical characteristics, which is the foundation of every digital and analog circuit ever manufactured.
Photolithography: Printing Circuits at Nanometre Scale
The manufacturing process begins with photolithography โ a technique borrowed from printing that exposes a light-sensitive chemical (photoresist) coated on a polished silicon wafer to ultraviolet light projected through a patterned mask. The unexposed regions are chemically dissolved, leaving the circuit pattern behind. Successive rounds of deposition, doping, and etching build up the complete transistor and wiring structure layer by layer. A modern logic chip requires more than 100 such process steps before the first electrical test.
The resolution of photolithography is governed by the wavelength of light used. Earlier generations used mercury arc lamps at 436nm and 365nm; later generations adopted excimer lasers at 248nm (KrF) and 193nm (ArF). Today's leading-edge production uses extreme ultraviolet (EUV) light at 13.5nm โ generated by firing a high-power COโ laser at liquid tin droplets โ which enables transistor gate lengths below 5nm. Each generation of lithography requires new equipment, photoresist chemistry, and optical infrastructure, which is why only a handful of companies worldwide can manufacture at the leading edge.
Package Types: From DIP to Ball Grid Arrays
Once fabricated, silicon dies are too small and fragile to handle directly. They are sawn from the wafer and encased in protective packages that route the chip's electrical connections to external pins. The Dual In-line Package (DIP), dominant from the 1970s through the 1990s, arranges pins in two parallel rows at 0.1-inch (2.54mm) spacing โ a dimension chosen specifically for breadboard compatibility that became an industry standard. Modern high-performance chips use Ball Grid Arrays (BGAs), where an array of solder balls on the package underside provides hundreds or thousands of connections in a footprint smaller than any through-hole equivalent could achieve.
BGAs allow finer pitch, better thermal performance through the substrate, and lower inductance connections โ critical at gigahertz operating frequencies where package parasitics become signal-integrity constraints. Quad Flat Packages (QFPs) occupy a middle ground: surface-mount leads extending from four sides, common in automotive and industrial applications where repairability matters. The choice of package type is rarely arbitrary; it reflects a deliberate optimisation of pin count, thermal resistance, signal frequency, and assembly yield for the target application.
2.5D and 3D Integration: Beyond the Single Die
The limits of single-die scaling have driven the industry toward multi-die integration. In 2.5D packages, multiple dies sit side-by-side on a shared silicon or organic interposer โ a passive wiring substrate that routes signals between them at densities unreachable with conventional printed circuit boards. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is the dominant 2.5D technology, used in virtually every AI accelerator currently in production. The interposer acts as a high-bandwidth interconnect fabric, enabling terabytes-per-second of data movement between a compute die and stacked memory.
3D-ICs go further, stacking dies vertically and connecting them through Through-Silicon Vias (TSVs) โ copper pillars etched through the full thickness of each layer. The result is a logic-on-logic sandwich with dramatically higher interconnection density than any planar arrangement allows. The primary engineering challenge is thermal: stacked dies trap heat between layers, and high-performance chips can dissipate over 200 watts in configurations where the bottom die receives heat from both below and above. Solving this requires novel thermal interface materials, embedded cooling structures, and careful floor-planning to distribute heat sources across the stack.
Published by Beamed Silicon Intelligence. Analysis reflects publicly available information as of publication date. Nothing herein constitutes investment advice.