The power requirements of AI accelerators have reached levels that expose fundamental limitations in traditional chip power delivery architectures. NVIDIA's Blackwell B200 GPU consumes between 700 and 1,400 watts depending on configuration โ more than a household microwave oven, delivered to a chip the size of a credit card. Supplying this power without unacceptable losses demands a complete rethink of how current moves from the package substrate into the active silicon, driving the industry toward backside power delivery networks that route supply lines below the wafer rather than competing with signals on the frontside.
The Frontside Power Delivery Bottleneck
In conventional chip architecture, power and signal interconnects share the same wiring layers on the frontside of the die. A modern high-performance logic chip may have 15 or more metal layers, with the upper layers carrying power rails and the lower, finer layers carrying signals. This arrangement forces power currents to route through the same congested interconnect stack as data signals, creating resistive losses that convert delivered power into heat and reduce the voltage actually reaching the transistors. At multi-kilowatt power levels, these losses become a significant fraction of total power consumption.
The problem compounds as technology nodes advance. Finer transistors require lower supply voltages โ today's leading-edge logic operates at 0.7โ0.8V โ which means the same power level requires proportionally higher currents. At 1V and 1,000W, the chip draws 1,000 amperes. The voltage drop across the wiring resistance at this current level can consume 10โ20% of the already-thin supply voltage, causing timing failures and requiring guardbands that reduce operating frequency. Traditional frontside power delivery over more than 10 wiring layers is becoming a fundamental performance limiter at leading-edge nodes.
Backside Power Delivery: Routing Current Below the Wafer
Backside Power Delivery Networks (BSPDN) address the frontside congestion problem by routing power supply lines on the underside of the wafer, completely separated from the signal interconnect stack. Power is delivered through the substrate into the backside of the chip via dedicated buried power rails and nano-TSVs, then distributed locally to transistor cells without competing with signal wires for routing resources. The result is lower IR drop, less supply voltage variation across the die, and more routing resources available for signals โ all translating to higher performance at the same power level.
TSMC demonstrated its PowerVia backside power technology in 2023, reporting a 10% performance gain and a 4% reduction in power consumption compared to an equivalent frontside-only design. Intel has integrated backside power in its 20A/14A process node under the PowerVia brand. The separation of power and signal routing also simplifies the process design kit and enables more aggressive cell library optimisation, since cell designers no longer need to route power rails through already-congested signal layers.
Materials Innovation: Molybdenum for Lower Contact Resistance
Alongside structural changes in power delivery, the industry is transitioning to new interconnect materials at the nanoscale. Tungsten has been the standard material for contacts โ the vertical conductors connecting transistors to the first metal layer โ since the 1980s, chosen for thermal stability and chemical compatibility with silicon. At advanced nodes, however, extremely small via dimensions below 10nm create conditions where tungsten's resistivity becomes problematic: the metal's bulk resistivity does not scale with geometry, but the geometry shrinks, so resistance rises.
Molybdenum is emerging as a replacement for tungsten contacts at advanced nodes. In geometries below 10nm, molybdenum offers up to 50% lower contact resistance than tungsten โ a significant gain where every milliohm of contact resistance contributes meaningfully to total power delivery resistance. TSMC, Samsung, and Intel have all disclosed molybdenum contact integration in their sub-2nm process research. The switch requires new deposition equipment and process integration, but the contact resistance improvement cascades directly into power delivery efficiency.
Published by Beamed Silicon Intelligence. Analysis reflects publicly available information as of publication date. Nothing herein constitutes investment advice.